Certain non-volatile memory devices may operate by trapping charges in a dielectric interface to adjust the threshold voltage of a transistor and thus program the desired digital value of the transistor. One method of trapping charges is found in nonvolatile flash devices that use a floating gate electrode layer placed between a tunnel oxide layer and a control oxide layer to trap charges under the influence of a control gate electrode. Other non-volatile memory devices may use ferro-magnetic or ferro-electric gate materials to program a digital value of the memory device. These types of memories can be programmed to be in either a high (i.e., logic level 1) state, or a low (i.e., logic level 0) state.
Some non-volatile memory devices may have a reliability issue with controlling current carrier flow through the dielectric layers from electrode to electrode due to the very thin physical thickness of the dielectric layers desired to obtain rapid current flow at reasonable voltage levels. For example, in a floating gate memory the top and bottom surfaces of each insulator layer may be in contact with a conductive surface, since each insulator layer may be located between solid conductive electrodes such as the substrate, the floating gate, and the control gate. Thus, a defect in either insulator layer may cause a device failure in a floating gate memory device. Charge trapping type non-volatile memories, such as NROM devices, use a change in dielectric properties, such as a boundary between two different dielectric materials, to create a layer of charge carriers, typically with an oxide-nitride-oxide (ONO) arrangement of three dielectric layers. This arrangement is less sensitive to dielectric defects in one of the three dielectric layers, but may have an issue with the programming and erasing voltage levels needed to obtain reasonable read and write speeds. It may also be difficult to obtain smooth surfaces for forming the remainder of the electronic device due to the tendency of each one of the three dielectric depositions to accentuate the particles and non-uniformities of the previous layer. This may result in electric field concentration and increased time dependent dielectric breakdown of the transistor.
The above noted issue of dielectric defect levels is likely to become more difficult in the future, since the semiconductor device industry has a market driven need to continue to reduce the size of semiconductor devices such as transistors in order to obtain lower power consumption and higher performance. In general, to reduce transistor size, the thickness of the silicon dioxide (SiO2) gate dielectric is reduced in proportion to the shrinkage of the gate length. For example, a metal-oxide-semiconductor field effect transistor (MOSFET) might use a 1.5 nm thick SiO2 gate dielectric for a gate length of 70 nm. An industry goal is to fabricate smaller, more reliable integrated circuits (ICs) for use in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs) and flash non-volatile memory.
The semiconductor industry relies on the ability to reduce the dimensions of its basic devices, generally known as scaling, to increase performance, decrease power consumption and decrease product costs of, for example, the silicon based MOSFET. This device scaling includes scaling the gate dielectric down to thinner layers, which may increase the above noted dielectric quality issue. The dielectric has primarily been silicon dioxide. This is because a thermally grown amorphous SiO2 layer provides an electrically and thermodynamically stable material, where the interface of the SiO2 layer with underlying silicon provides a high quality interface as well as superior electrical isolation properties. A further potential issue with scaling memory transistors to lower levels may be electrical leakage due to the small gap from source to drain diffusion.
It is possible to use phase change materials as a memory device. Phase change materials have a different electrical resistance in a polycrystalline phase as compared to an electrical resistance in an amorphous phase, and such phase change materials may be changed from a crystalline state (equivalent to an on state, for example a 1 state) to an amorphous state (equivalent to an off state, for example a 0 state) by the use of diodes rather than transistors, and thus may be more scalable than present memory cells containing transistors. Such phase change memory cells are not as sensitive to scaling related problems, such as dielectric leakage and punch through leakage, as are the MOSFETs currently used in most memory devices.
The use of memory cells that may be programmed reliably to more than just a single on state and a single off state may be used to greatly reduce the number of memory cells to store a given amount of data. For example, a memory cell that could be programmed to have eight distinct levels, each representing a distinct state, would allow the number of memory cells to be reduced to one third of the number of binary memory cells of the type such as those discussed above. Thus, there may be a benefit to the industry of a method to form a non-volatile memory device that possess more programmable logic states than the above noted practice in the industry of two logic states, as may be found in binary systems, and a non-volatile memory device that may be scaled down in size without encountering the long term reliability issues found in transistor memory devices.